No of students per batch : Upto 30
Course Duration: 6 months (1000 hrs)
No of students per batch : Upto 30
Course Duration: 6 months (1000 hrs)
Design and deliver custom training solutions meeting your company needs.
Successfully delivered training for CISCO, ARM, MENTOR GRAPHICS, PHILIPS, WIPRO, NXP Semiconductors and Cortina.
450+ Engineers trained, that included both Experienced and Entry Level Professionals,Over 2000 Hours of Structured Training Delivered
This one-day class is a general introduction to the VHDL language and its use in programmable logic design, covering constructs used in both the simulation and synthesis environments. By the end of this course, you will have a basic understanding of VHDL so that you can begin creating your own designs, using both behavioral and structural approaches.
International (Corporate) Fee: $ 495
Domestic (Corporate) Fee: INR 5,000
Domestic (Student) Fee: INR 3,500
For further details contact RV-VLSI
In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.
This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in both the simulation and synthesis environments. By the end of this course, you will have a basic understanding of the Verilog module, data types, operators and assignment statements needed to begin creating your own designs, using both behavioral and structural approaches.
International (Corporate) Fee: $ 495
Domestic (Corporate) Fee: INR 5,000
Domestic (Student) Fee: INR 3,500
For further details contact RV-VLSI
In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.
This course cover Electrical /Electronic (E/E) architecture, sensing technologies, actuation, embedded controller development, Powertrain management, chassis control systems, electric vehicle, body electronics, safety, networking, telematics & diagnostics.
The course contents are designed keeping the industry requirements in mind. Each student will get the opportunity to learn product design from first principles and have adequate time to learn by designing using industry approved software and hardware development platform. An integral part of this program is to work in teams where each team designing a specific module, this will give the students valuable insights into how professionals work in the industry and the interdependencies across teams to achieve a commercially viable product.
Highlights::
Module-1: Introduction to Vehicle Mechanics.
This module will help students to gather knowledge of mechanical structure, aggregates and sub systems of a vehicle. This understanding is crucial to implement features using electronics.
Module-2: Vehicle E & E architecture.
This module will provide an overview of electrical systems and communication networks used to handle power, signal and data flow across electronic control units (ECU) in the entire vehicle.
Module - 3: Sensors & Actuators
This module will provide basic understanding of sensing and actuation technology covering working principle, installation scheme, connectivity, and calibration. The key takeaway from this module is to understand how to select a correct type of sensor from a range of sensors for a particular application
Module - 4 Introduction to Embedded controller (Electronic control unit) development
All the vehicle electronic modules and circuits are based on microcontroller architecture. Students will understand multi core concepts, memory management, peripherals handling and selection criteria, which are essential to design, implement and realize various control functions in a vehicle. Further, this will help in understanding logic frame work to translate requirements to functions. Also, Illustrate development process in easy steps to realize control and monitoring functions
Module-5: Vehicle Mechatronic systems
Mechanical subsystems of Modern vehicles are automated using electronic circuits. The area of specialization is commonly called Mechatronics. This module provides insights to the Principles, techniques and control strategy deployed in controlling wide range of vehicle mechanical systems
Module-6: Electric powertrain
Rapid transformation to produce Zero emission vehicle is the current trend in providing clean mobility solutions. Global regulatory requirements will be the key driver in accelerating electric vehicles deployment across all geographical locations. This module will help students in understanding power electronics, motors and battery management required for electric vehicle building
Module- 7: Telematics
In the near future, ownership model of vehicles will change from the current model. Since 90% of the time vehicles are parked unused, there is a compelling need to change this and increase the ROI for vehicle owners. With the advancement of Machine /Artificial learning (ML/AL) and newer electronics components Vehicle availability and utilization optimization for efficient fleet management is possible. This module helps in understanding On - board telematics system along with back end data analytics to provide real time vehicle status.
Module-8: Need for Testing & validation of vehicle electronics
It is required that automotive electronics shall perform reliably under all operating severities. Also, rapid increase in the sophistication of vehicle automation demands development of new cost effective, reliable and quick testing technologies to understand and evaluate driver-automation interaction.
Module-9: Futuristic technologies
The future of vehicles will comprise more of Electrical and electronics devices and less of Mechanical engines. Emerging technologies in VLSI, Embedded Systems, Artificial Intelligence and Machine Learning has made it possible to achieve a high degree of automation and enhance the driving and user experience. Sophisticated technology is already active in vehicle control like driver assistance, lane keeping, Auto parking, speed maintenance, blind spot monitoring and self - driving technology
Project work
Design and development of control & monitoring features will be under following verticals
Tools used
Complex VLSI designs support many features. Ensuring the RTL Design is bug free before it is convereted to a netlist is the job of a RTL Verifiction engineer.
System Verilog is used widely to verify the functional correctness of VLSI design.
- Familiarity with Logic Design concepts
-Familairity with Verilog Syntax
- Prior knowledge of RTL Verification concepts usingVerilog is desirable
- VLSI Engineers seeking lateral shift from FPGA to ASIC front-end jobs
- Engineers looking for RTL verification jobs.
- Engineers familiar with RTL verification using Verilog looking to acquire skills in System Verilog
(1) Introduction to SV
(2) Commonly Used Terminologies in SV
(3) Data Types
(4) Object-Oriented Programming (OOP) Concepts
(5) SV Stratified Event Queue/Scheduler
(6) SV Tasks and Functions
(7) Verification Specific SV Constructs
(8) Functional Coverage
(9) Verification Plan and SV Testbench Architecture
(10) Modelling Testbench Blocks
12 days, Rs.36000+ Taxes
ADEMS is a 16 weeks full time program designed to meet the requirements of the current job market. The program comprises of two phases. Phase one covers the fundamental concepts in Embedded Systems and domain specific modules. Phase two is the project phase where you get an opportunity to apply design concepts learnt in phase one by working on real life projects under the supervision of industry experts. The contents of the course are designed to make you eligible to apply for hardware designer, software developer, firmware developer and network stack developers job openings. A key differentiator of our program is the introduction of advanced microcontrollers and use of multiple hardware boards in the course.
Hardware Software Integration
Designing a VLSI chip using FPGA's are very popular these days.
This program is a foundation course for working professionals looking for a job change to the core industry and for engineers in the core industry looking for a lateral change.
This program introduces you to the concepts of system design, RTL design using Verilog, programmable ASICs and the role of programmable ASICs in design and development of high density complex IP designs. The course also focuses on the real and practical scenarios using modern FPGA architectures. The course will conclude with an industry oriented project work under the supervision of our expert leads.
- Understanding of Logic Design concepts
- Familiarity with Verilog Syntax
- BE (Elens and related branches), Engineers working in software domain looking for core jobs
- VLSI Engineers seeking lateral shift to a front end job.
(1) Overview of Digital Logic Design
(2) Introduction to Verilog HDL
(3) Advanced Verilog Design Techniques
(4) Basics of Programmable Logic
(5) How to begin Simple FPGA Design
(6) Design Implementation using Altera Quartus II
(7) Efficient Design Practices using Altera Quartus II
(8) Project work and board bring up
8 days, Rs. 19250 +Taxes
* Industry standard sign-off tools from multiple EDA vendors.
* All courses will be delivered by VLSI professionals with hands on experience taping out multiple chips used in industry.
Course Description
Our flagship VLSI program, it covers FPGA, ASIC Frontend, ASIC Backend and Full Custom design methodologies giving you an option to specialize as a RTL Verification Engineer, ASIC Physical Design Engineer or Full Custom Memory and/or Physical IP Engineer. To the best of our knowledge no other skill development program in India cover all these domains
Students who gain admission to this program are job ready for FPGA, ASIC and/or Full-custom Analog domains
Product companies, Service companies, EDA tools providers and IP companies regularly visit our campus to hire engineers who have successfully completed this program
We have one of the best placement assistance programs; enquire at the center for details.
Duration: 6 months full-time program.
Please enquire at the center for other details.
IC Layout design methodology is used to design the layouts of Physical IP such as Standard Cells, Memory cells, IO’s and analog blocks which are used in a VLSI chip.
This program introduces you to the layout design and optimization techniques commonly used in the industry to design layouts for DSM process nodes. Industry standard EDA tools will be used extensively.Topics such as Device Matching, DFM, Latch-up and ESD guidelines are covered.
Every participant will get the opportunity to practice concepts taught in the class during the concept labssessions. The course will conclude with a project done under the supervision of our leads.
- Basic undestanding of MOS Transistor operation
- VLSI Engineers seeking lateral shift as Full Custom/Mask Layout Engineer
- Engineers looking to work in areas like Physical IP & Full Custom Analog Layout design
(1) Overview of Full custom IC design
(2) Review of Simple circuits
(3) Overview of IC Fabrication Process
(4) Introduction to Polygon Editors
(5) Layout design concepts
(6) Introduction to ESD, LUP, Device Matching techniques and PDK’s
(7) Physical Verification and Parasitic Extraction
(8) Project Work
12 days, Rs.42000+Taxes
In this class,youwill improve your proficiency in writing Synopsys Design Constraint (SDC) files and performing timing analysis using the TimeQuest timing analyzer in the Quartus® II software v. 11.1. You will also learn how to automate the process of constraining and analysis by writing customized Tcl script files.
International (Corporate) Fee: $495
Domestic (Corporate) Fee: INR 5,000
Domestic (Student) Fee: INR 3,500
For further details contact RV-VLSI
In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.
Learn the best ways to maximize productivity throughout the FPGA design cycle, while also maximizing design performance. Using a recommended design methodology as a framework, see what is involved at a high level in preparing to create an FPGA design and what is required to implement it - from the creation of the design specification all the way to final sign-off.
International (Corporate) Fee: $990
Domestic (Corporate) Fee: INR 10,000
Domestic (Student) Fee: INR 5,500
For further details contact RV-VLSI
In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.
In this class,youwill learn advanced features of the Quartus® II design software v.11.1 that will enable you to shorten your design cycle as well as improve your design performance and utilization.
International (Corporate) Fee: $ 495
Domestic (Corporate) Fee: INR 5,000
Domestic (Student) Fee: INR 3,500
For further details contact RV-VLSI
In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.
This course will teach you how to design in a soft core embedded processor with an Altera FPGA. This course is focused on the hands-on development of Nios® II processor-based systems using a Nios II Development Kit. You will learn how to integrate a Nios II 32-bit microprocessor and test it in an Altera FPGA.
International (Corporate) Fee: $ 990
Domestic (Corporate) Fee: INR 10,000
Domestic (Student) Fee: INR 5,500
For further details contact RV-VLSI
In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.
This course is targeted at Software Engineers or Developers. You will learn to develop and run embedded software for the Nios® II processor in the Nios II Software Build Tools for Eclipse and with the Nios II Command Tools.
International (Corporate) Fee: $ 990
Domestic (Corporate) Fee: INR 10,000
Domestic (Student) Fee: INR 5,500
For further details contact RV-VLSI
In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.
This class will teach you how to quickly build designs for Altera FPGAs using Altera’s Qsys system-level integration tool. You will learn how to build hierarchical systems, how to quickly integrate IP and custom logic into a system, and also how to optimize designs for performance. Since Qsys makes design reuse easy through standard interfaces, we will dive deeply into the Avalon-Memory Mapped and Streaming Interfaces.
International (Corporate) Fee: $ 990
Fee: INR 10,000
Domestic (Student) Fee: INR 5,500
For further details contact RV-VLSI
RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.
In this class,youwill learn & practice efficient coding techniques for writing synthesizable VHDL for programmable logic devices (FPGAs & CPLDs). While the concepts presented will mainly target Altera® FPGA devices using the Quartus® II software, many can be applied to other devices & synthesis tools.
International (Corporate) Fee: $ 495
Domestic (Corporate) Fee: INR 5,000
Domestic (Student) Fee: INR 3,500
For further details contact RV-VLSI
In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.
In this class, you will learn how to constrain & analyze a design for timing using the TimeQuest timing analyzer in the Quartus® II software v. 11.1. You will see how the TimeQuest timing analyzer makes it easy to create timing constraints to help you meet those requirements.
International (Corporate) Fee: $ 495
Domestic (Corporate) Fee: INR 5,000
Domestic (Student) Fee: INR 3,500
For further details contact RV-VLSI
In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.
Static Timing Analysis is one of the critical steps in the ASIC design flow. The timing correctness of the design is checked in this step.
This program introduces the timing concepts needed to verify the timing correctness of ASIC Design Blocks.
Timing issues typical to Deep sub-micron process nodeswill be covered in detail. Industry standard tools will be used in the labs. Importance of design constraints, timing exception, Setup and Hold checks for multimode multi corners will be discussed. OCV and AOCV issues are covered. Due focus on Signal Integrity and pre and post layout timing validation is given.
Each participant will get the opportunity to practice concepts taught in the class during the concept labssessions followed by verifying the timing reports for a ASIC block of moderate complexity
- Logic Design
- MOS Transistor Theory
- VLSI Engineers seeking lateral shift to a back end job.
- Engineers looking to work for Block level Physical Design Implementation, Place and Route job profiles.
(1) Concepts of STA
(2) Clocks & Virtual Clocks
(3) Operating Conditions,
(4) Analysis of various Modes & Corners
(5) Analyzing the Timing Reports
(6) Signal Integrity
12 days, Rs.36000+Taxes
* Industry standard sign-off tools from multiple EDA vendors.
* All courses will be delivered by VLSI professionals with hands on experience taping out multiple chips used in industry.
The last phase in the ASIC Design flow involves designing the layout of a Gate Level Netlist using Automatic Place and Route (AP&R) Tools
This program introduces you to the concepts used to design Chip-level and Block Level ASIC Layoutsfor Deep sub-micron process nodes using industry standard AP&R (Synopsys) tools. The various implementation steps from Netlist to GDS2 will be covered in detail. Every participant will get the opportunity to practice concepts taught in the class during the concept labssessions. The course will conclude with a project done under the supervision of our leads.
- Logic Design
- Course on Static Timing Analysis
- VLSI Engineers seeking lateral shift to a back end job.
- Engineers looking to work for Block level Physical Design Implementation, Place and Route job domains.
(1) Introduction to the ASIC Flow
(2) Design Setup
(3) Chip-Level and Blocl-level implementation steps
(4) Floorplan and power planning
(5) Placement and Clock Tree Synthesis,
(6) Routing, Physical Verification and DFM checks
(7) Signal Integrity and Backannotation
(8) Sign-off checks and Tapeout/Hand0ff
12 days, Rs.42000+Taxes
* Industry standard sign-off tools from multiple EDA vendors.
* All courses will be delivered by VLSI professionals with hands on experience taping out multiple chips used in industry.
In this class,youwill learn & practice efficient coding techniques for writing synthesizable VHDL for programmable logic devices (FPGAs & CPLDs). While the concepts presented will mainly target Altera® FPGA devices using the Quartus® II software, many can be applied to other devices & synthesis tools.
International (Corporate) Fee: $ 495
Domestic (Corporate) Fee: INR 5,000
Domestic (Student) Fee: INR 3,500
For further details contact RV-VLSI
In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.
By attending The Quartus II Software Design Series: Foundation course, you'll learn how to use the Quartus® II software v11.1 to develop an FPGA or CPLD design from initial design to device programming.
International (Corporate) Fee: $ 495
Domestic (Corporate) Fee: INR 5,000
Domestic (Student) Fee: INR 3,500
For further details contact RV-VLSI
In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.
In this class, you will learn features of the Quartus® II software v. 11.1 that will enable you to analyze and debug your Altera® design. You will get to understand power analysis tools, and other tools like Simultaneous Switching Noise (SSN) Analyzer, SignalTap® II embedded logic analyzer, Signal Probe & the Logic Analyzer Interface. You will learn to analyze and make changes to your design using the Chip Planner.
International (Corporate) Fee: $ 495
Domestic (Corporate) Fee: INR 5,000
Domestic (Student) Fee: INR 3,500
For further details contact RV-VLSI
In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.
1. Three months AE concepts, power electronics basics, simulation and modeling
2. Three months in following domains including industry relevant project
For more information please contact at Email: info@rv-ae.com, Ph: +91-80-4078 8574
